In transferring data to a predetermined transmission line or in recording data onto a recording medium, such as a magnetic disk, an optical disk, or a magneto-optical disk, the data is modulated to suit the transfer or recording. One known modulation method is block coding. Block coding is to divide a data stream into blocks of m×i bits (hereinafter the blocks are referred to as data words), and each data word is converted into a codeword of n×i bits in accordance with an appropriate coding rule. When i=1, the resultant code is a fixed-length code. When i can be of multiple values, that is, when i is selected from a range of 1 to i max (maximum i) and conversion is performed with the selected i, the resultant code is a variable-length code. The code generated by block coding is defined as a variable-length code (d, k; m, n; r).
In the above description, i denotes the constraint length, and i max is r (maximum constraint length); d denotes the minimum number of consecutive “0s” between consecutive “1s”, e.g., the minimum run length of “0”; and k denotes the maximum number of consecutive “0s” between consecutive “1s”, e.g., the maximum run length of “0”.
In recording the code generated as described above onto an optical disk, a magneto-optical disk, or the like, such as a compact disk (CD) or mini disk (MD), the variable-length code is subjected to NRZI (Non Return to Zero Inverted) modulation in which “1” is inverted whereas “0” is not inverted, and recording is done on the basis of the NRZI-modulated variable-length code (hereinafter referred to as the recording code string). There is a system, such as that on a magneto-optical disk in an initial ISO format having a not-so-high recording density, which records a modulated recording bit string that has not been subjected to NRZI modulation.
The minimum inversion interval of the recording code string is denoted by Tmin, and the maximum inversion interval of the recording code string is denoted by Tmax. Higher recording density in the direction of linear velocity is realized when the minimum inversion interval Tmin is longer, that is, when the minimum run length d is greater. On the other hand, in terms of clock reading, it is preferable to have a shorter maximum inversion interval Tmax, that is, a smaller maximum run length k. Various modulations methods have been proposed.
Specifically, modulation systems proposed or actually used in, for example, optical disks, magnetic disks, magneto-optical disks, and the like are described as follows.
For example, RLL codes (Run Length Limited Code) with the minimum run length d=2 include an EFM (Eight to Fourteen Modulation) code (may also be represented as (2, 10: 8, 17; 1)) used in CD, MD, and the like; an 8-16 code (may also be represented as (2, 10: 8, 16; 1)) used in DVD (Digital Video Disk); an RLL (2-7) (may also be represented as (2, 7; 1, 2; r)) used in PD (Phase Change Disk); and the like.
RLL codes with the minimum run length d=1 include a fixed-length RLL (1-7) (may also be represented as (1, 7; 2, 3; 1)) used in an ISO-format MO disk (Magnetic-Optical Disk); and a variable-length RLL (1-7) (may also be represented as (1, 7; 2, 3; r)) used in a disk drive for a high-density optical disk, magneto-optical disk, or the like.
A conversion table for the variable-length RLL (1-7) is as follows:
TABLE 1RLL (1, 7, 2, 3, 2)Data wordCodewordi = 11100x100100110xi = 20011000 00x0010000 0100001100 00x0000100 010
The symbol x in the conversion table corresponds to 1 when the subsequent codeword is 0 and corresponds to 0 when the subsequent codeword is 1. The maximum constraint length r is 2.
The parameters of the variable-length RLL (1-7) are (1, 7; 2, 3; 2). When the bit interval of the recording code string is denoted by T, the minimum inversion interval Tmin expressed as (d+1) is 2(=1+1)T. When the bit interval of the data stream is denoted by Tdata, the minimum inversion interval Tmin expressed as (m/n)×2 is 1.33(=(2/3)×2)Tdata.
In the above description, m/n denotes conversion at the ratio m:n. For example, ⅔ denotes conversion at 2:3 (conversion of a data word of 2×i bits into a codeword of 3×i bits).
The maximum inversion interval Tmax expressed as (k+1)T is 8(=7+1)T ((=(2/3)×8 Tdata=5.33 Tdata). The detection window margin Tw is expressed as (m/n)×Tdata and is 0.67(=2/3)Tdata.
In a code string (channel bit string) generated by RLL (1-7) modulation in Table 1, 2T which is Tmin occurs most frequently, which is followed by 3T, 4T, and so forth. The fact that edge information, such as 2T or 3T, occurs many times with a short cycle is advantageous in reading clock.
In contrast, when the recording linear density becomes higher, the minimum run length causes a problem. Specifically, when 2T (the minimum run length) occurs consecutively, the recording waveform is easily distorted because the waveform output of 2T is smaller than the others and is influenced more easily by defocus, tangential tilt, or the like.
In recording at high linear density, recording with consecutive minimum marks is influenced more easily by disturbance, such as noise, and this may easily lead to a data read error. In such a case in which a data read error occurs, the error often resides in shift of start-edge and end-edge of the consecutive minimum marks. In other words, the generated bit error length becomes longer.
In order to solve this problem, the consecutive minimum run lengths are controlled to better suit high linear density.
In contrast, in recording onto a recording medium or in data transfer, code modulation based on each medium (transfer) is done. When a modulated code contains a DC component, fluctuation or jitter may be caused in various error signals, such as for a tracking error in servo control of a disk drive. It is preferable for the modulated code not to contain a DC component.
In order to solve this problem, DSV (Digital Sum Value) control is proposed. DSV is the sum of bits of an NRZI-modulated (level-coded) bit string (channel bit string) in which “1” corresponds to +1 and “0” corresponds to −1. DSV serves as a reference for a DC component in the code string. Minimizing the absolute value of DSV, that is, performing DSV control, enables suppression of a DC component in the code string.
In the code modulated according to the variable-length RLL (1-7) table shown in Table 1, no DSV control is performed. In such a case, DSV control is performed by calculating DSV of the modulated channel bit string at a predetermined interval and inserting predetermined DSV control bits into the code string.
Basically, the DSV control bits are redundant bits. In view of the efficiency of code conversion, the fewer the DSV control bits, the better.
It is preferable that the minimum run length d and the maximum run length k remain unchanged by the inserted DSV control bits. Changes of (d, k) influence the reading and writing characteristics.
In order to satisfy the above requirements, DSV control must be performed in as efficiently as possible.
While the actual RLL code must satisfy the minimum run length requirement, the maximum run length requirement need not be satisfied. There is a format that uses a pattern exceeding the maximum run length for a sync signal. For example, although EFM plus for DVD has a maximum run length of 11T, EFM plus for DVD allows for 14T as a matter of convenience of the format. By exceeding the maximum run length, for example, the capability of detecting a sync signal or the like is enhanced greatly.
In the RLL (1-7) format with improved conversion efficiency, it is important to “control the consecutive minimum run lengths so as to better suit the high linear density” and to “perform DSV control as efficiently as possible” in association with an increase in linear density.
Accordingly, the assignee of the present invention et al. discloses, in Japanese Patent Application No. 10-150280, a conversion table including, as a conversion code, a basic code where d=1, k=7, m=2, and n=3; a coding rule that the remainder of the number of “1s” in each element of a data stream divided by two must be one or zero and equal the remainder of the number of “1s” in a converted channel bit string divided by two; a first replacement code for limiting the consecutive minimum run lengths d to a predetermined number or less; and a second replacement code for satisfying the run length limitation.
Specifically, when a disk drive with high linear density reads/writes an RLL code, a pattern with consecutive minimum run lengths often causes a long error.
When DSV control is performed on an RLL code, such as the RLL (1-7) code, DSV control bits need to be inserted into a code string (channel bit string) at arbitrary intervals. As described above, since the DSV control bits are redundant bits, it is preferable to have fewer DSV control bits. In order to maintain the minimum run length or the maximum run length, the DSV control bits of at least 2 bits or greater are necessary.
The assignee of the present invention et al. discloses, in Japanese Patent Application No. 10-150280, an RLL code with the minimum run length d=1 (d, k; m, n) and a conversion table, which is shown in Table 2, for limiting the number of consecutive minimum run lengths and for performing complete DSV control using efficient control bits while maintaining the minimum run length and the maximum run length (hereinafter referred to as a 1,7PP table; and a code according to 1,7PP table is referred to as a 1,7PP code):
TABLE 21, 7PP(d, k, m, n, r) = (1, 7, 2, 3, 4)Data wordCodeword11*0*10001010100011010 1000010010 0000001000 100000011000 100 100000010000 100 000000001010 100 100000000010 100 000“110111001 000 000 (next010)00001000000 100 100 10000000000010 100 100 100if xx1 then *0* = 000 xx0 then *0* = 101Termination table000000000010 100“110111001 000 000 (next010)When next channel bits are ‘010’convert ‘11 01 11’ to ‘001 000 000’ afterusing main table and termination table.
As an example of a modulation apparatus using the 1,7PP table, the assignee of the present invention discloses, in Japanese Patent Application No. 10-150280, a modulation apparatus 1 shown in FIG. 1.
The modulation apparatus 1 includes a DSV control bit determination and insertion unit 11 for determining “1” or “0” serving as a DSV control bit and inserting the DSV control bit into an input data stream at arbitrary intervals; a modulator 12 for modulating the data stream containing the DSV control bits; and an NRZI unit 13 for converting the output of the modulator 12 into a recording code string. Although not shown in the diagram, the modulation apparatus 1 includes a timing management unit for generating a timing signal, supplying the timing signal to the above components, and managing timing.
In Japanese Patent Application No. 09-342416, the assignee of the present invention et al. discloses a specific example of another modulation apparatus, namely, a modulation apparatus 2 shown in FIG. 2.
The modulation apparatus includes a DSV control bit insertion unit 21 for inserting “1” or “0” serving as a DSV control bit into a data stream at arbitrary intervals. At this time, there is a data stream into which the DSV control bit “1” is inserted and another data stream into which the DSV control bit “0” is inserted. The modulation apparatus further includes a modulator 22 for modulating the data stream containing the DSV control bits and a DSV controller 23 for NRZI-modulating the modulated code string into level data, calculating DSV of the level data, and consequently outputting a DSV-controlled recording code string.
As described above, the 1,7PP code is advantageous in solving the above problems. In contrast, compared with a modulation apparatus using a known method or a technique for performing DSV control on the RLL (1,7) code, the configuration of the known modulation apparatus using the 1,7PP code is complicated, and the circuit size is increased.
For example, in the modulation apparatus 2 shown in FIG. 2, the register configuration in the modulator 22 is shown in FIG. 3. Specifically, the modulator 22 has a modulation (1,7PP modulation) portion and a delay portion corresponding to a DSV control interval (DSV section) in one integrated unit in order to transfer data corresponding to the DSV control interval to the DSV controller 23 at a subsequent stage. As a result, the modulator 22 needs two registers, that is, an input register 22a (register 22a for the data stream) and an output register 22b (register 22b for the channel bit string). The number of registers required corresponds to the DSV control interval. Two pairs of registers (registers 22a and 22b) are necessary for the DSV control bit “0” and the DSV control bit “1”.